In digital to analog conversion ("DAC"), an analog output is generated by summing weighted currents corresponding to the various bits of a digital signal. A major cause of distortion in this analog output is the asymmetry, or skew, in the on and off switching times of these bit currents. For example, glitches may occur in the analog output when attempting to simultaneously turn some bit currents on and others off. The glitches result if all of these bit currents are momentarily on, causing larger than expected output current, or off, causing less than expected output current, before reaching their final states. For typical DAC architectures, the glitch distortion is worst at mid-scale, since this is where the largest opposing currents are being switched.
Asymmetry of bit current switching times also causes pulse width distortion. For example, a DAC input designed to produce a square wave output will actually cause an output with non-50% duty cycle. Although not as readily observable, the performance limitations of this distortion are of the same order of importance as the glitch distortion. The effects of both glitch and pulse width distortion increase as the conversion clock frequency increases, since the distorted time interval is constant, and this becomes a greater percentage of the clock period.
Both glitch and pulse width distortion can severely degrade DAC performance in certain applications. For example, in direct digital synthesis systems, digital to analog converters are used for sine wave reconstruction. In these systems, spectral purity of the output sine wave is often the most important consideration, and DAC performance is frequently the limiting factor. Both glitch and pulse width distortion produce harmonics of the intended sinewave. At low clock frequencies, where the distorted interval is a small percentage of the period, other effects will dominate, such as DC non-linearity. However, at high frequencies, skew distortion may become dominant, and is compounded for output frequencies greater than one-fourth of the conversion frequency, since the frequency of the aliased second harmonic can become very close to the output frequency and thus difficult if not impossible to filter out.
Existing techniques for minimizing these distortion effects present significant drawbacks. Such techniques include careful matching of critical path delays, switching threshold adjustments, or combinations of these approaches. Another technique is to use small off-chip capacitors on each of the three or four most significant bits. These techniques, however, are dependent upon process variations and changing operating conditions (such as power supply variations, voltage swings and temperature effects). With changing operating conditions, repeated adjustments are often required, and unpredictable performance results.
Therefore, a need has arisen for a method and apparatus for digital to analog conversion with minimized distortion that provides optimum performance over a wide range of process variations and operating conditions.